1. Field
Exemplary embodiments of the present invention relate to a full adder circuit, and more particularly, to a full adder circuit outputting a carry value.
2. Description of the Related Art
A full adder circuit is a basic element widely used for a digital signal processing system including an operation system. The full adder circuit is well used in novel data processing scheme for rapidly processing a large amount of information signals. Circuit design is one of main concerns for a full adder circuit improving the data processing speed in an operation system or a data processing system rapidly processing a large amount of information signals.
FIG. 1 is a circuit diagram illustrating a full adder of prior art.
Referring to FIG. 1, the full adder is a logic circuit for generating 2 outputs for 3 input bits. The 3 input bits are 2 input signals SIG_A and SIG_B and a carry input signal SIG_CIN. The full adder outputs a sum signal SIG_SUM and a carry output signal SIG_COUT. The full adder includes 2 XOR gates and 3 NAND gates.
As illustrated in FIG. 1, a first XOR gate XOR1 performs XOR operation for the input signals, for example, a first and a second input signals SIG_A and SIG_B and generates a logic high level signal, i.e., ‘1’ when the input signals do not have the same logic level to each other. A second XOR gate XOR2 performs XOR operation for the output of the XOR gate XOR1 and the carry input signal SIG_CIN to generate the sum signal SIG_SUM. A first NAND gate NAND1 performs NAND operation for the output of the XOR gate XOR1 and the carry input signal SIG_CIN. A second NAND gate NAND2 performs NAND operation for the first and second input signals SIG_A and SIG_B. A third NAND gate NAND3 performs NAND operation for the outputs of the first and second NAND gates NAND1 and NAND2 to generate the carry output signal SIG_COUT.
As disclosed above, the full adder of prior art includes 3 NAND gates, each of which has 4 transistors, which means that the full adder of prior art has 12 transistors and leads to inefficiency in terms of tendency of high-integration. A number of the full adder or the transistors increases as a number of input signals for operation increases, which may cause an increase in chip layout size and a threshold pass delay in the circuit and thus a concern on the performance of the data processing system.